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Elettronica Digitale
Digital Electronics
Giorgio Biagetti

Seat Ingegneria
A.A. 2016/2017
Credits 9
Hours 72
Period I
Language ENG

Prerequisites
knowing how to analyze linear and non-linear electronic circuits, behavior of semiconductor devices, boolean algebra, mathematical analysis.

Learning outcomes
KNOWLEDGE AND UNDERSTANDING:
The students will start to know and understand the behaviour and the inner workings of digital electronic circuits (logic gates, arithmetic, addressing, and sequential circuits, memories), as well as the basis of their design, either with discrete components, with integrated circuits, and by means of programmable systems.
CAPACITY TO APPLY KNOWLEDGE AND UNDERSTANDING:
Students must be able to design digital electronic circuits, both by chosing discrete components from available commercial offerings, and in integrated circuit form, by drafting layouts of simple circuits. The student must also be able to apply the acquired knowledge to understand the most commonly employed electronic buses, and to analyze/simulate programmable systems described in languages such as VHDL.
TRANSVERSAL SKILLS:
The solution of real-world design problems stimulates the student's ability to integrate knowledge acquired in this and in the preceding courses, so as to reach a complete and rational design solution based on the available scientific literature and the device data sheets.

Program
Elementary CMOS logic gates: NMOS and CMOS inverters. DC and transient characteristics. Design criteria. Power dissipation. CMOS buffers. Complex CMOS logic gates: NAND, NOR. DC characteristics, design formulas. CMOS transient: RC approximation, Elmore method. Mirror circuits: XOR and XNOR gates. Transmission Gates: nFET and pFET switch, clock feedthrough, CMOS switch. XOR and XNOR gates. Tristate and open-drain gates. Elementary BJT logic gates. RTL, DTL and TTL inverters. Transfer characteristics. NAND and NOR TTL gates. TTL-CMOS interfaces. BiCMOS inverter. Combinatorial circuits: binary decoders. multiplexer, demultiplexer. PLD: logic array, AND and OR. PLA. Wired-and logic. Arithmetic circuits: adders, subtracters, multipliers, comparators, shifters. Sequential circuits: bi-stable circuits, latches and flip-flops. Master/Slave configuration. Finite state systems (FSS): design and minimization of the number of states. Programmable devices: CPLD and FPGA architecture and design methods. Elements of VHDL. Memories: organization, decoder, basic memory cell, sense amplifier. CMOS static RAM: 6 transistor cell. Dynamic RAM: 1 transistor cell. Non-volatile memories: FLASH and EEPROM. Memory interfaces: parallel (SRAM, DRAM, NAND) and serial (SPI, I2C) buses. Design guidelines: synchronous circuits, clock buffering, synchronizers, reset, test circuits and interfaces.

Development of the examination
LEARNING EVALUATION METHODS
The evaluation method comprises two tests: - a two-hour written paper, which proposes five relatively short exercises to be solved. The exercises may deal with both design and analysis problems related to the circuits and the topics covered during the lectures; - an oral test, which includes the discussion of the written paper and of some of the other topics dealt with in the course. If necessary, the level of knowledge of the essential prerequisites for mastering the subject may also be tested. Passing the written test with at least half of the maximum mark is considered a propaedeutic step in facing the oral test. The oral test must be undertaken during the same exam session as the written test. If the oral test is failed, the student is then required to repeat the written paper as well.

LEARNING EVALUATION CRITERIA
The two tests aim at evaluating both the completeness of the knowledge acquired by the student on the subject and the topics covered during the course, and the student's ability of applying the acquired knowledge to the solution of engineering problems regarding the design and the analysis of digital circuits.

LEARNING MEASUREMENT CRITERIA
Each exercise in the written paper is assigned a predetermined, although variable, maximum mark, typically ranging from 4 to 8 according to the exercise difficulty. The sum of the maximum marks of all of the exercises exceeds 30 by about 10%-15%, though the maximum mark assigned to the whole written paper is still limited to 30. For the exercises that require numerical results, half of the available marks will be assigned according to the correctness of the numerical results, the other half according to the correctness and completeness of the solution procedure adopted by the student. The final mark of the written test will be the sum of the marks obtained in the individual exercises, limited to 30 if the sum exceeds this threshold. The oral test will directly be evaluated with a mark from 0 to 30.

FINAL MARK ALLOCATION CRITERIA
Since the oral test includes the discussion of the written paper, the final mark will be the mark obtained in the oral test. Honors will be granted to students that, having obtained the maximum mark in the oral test, have also demonstrated an excellent mastering of the subject and the ability of facing problems even if not directly discussed during the lectures. The mark obtained in the written paper is only used as a preliminary evaluation that can be used by the student to assess their preparation, and as a starting point to direct the beginning of the oral test.

Recommended reading
Travis N. Blalock, Richard C. Jaeger, “Microelettronica: 3. Elettronica digitale”, McGraw-Hill Paolo Spirito, “Elettronica Digitale“, McGraw-Hill John P. Uyemura, “CMOS Logic Circuit Design”, Kluwer Academic Publishers Franco Fummi, Maria Giovanna Sami, Cristina Silvano, “Progettazione Digitale“, McGraw-Hill Lecture notes by the teacher, available through the university's moodle platform.

Courses

• Ingegneria Elettronica (Corso di Laurea Triennale (DM 270/04))